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GENLINX TMII GS9032
Digital Video Serializer
DATA SHEET FEATURES * SMPTE 259M and 540Mb/s compliant * serializes 8-bit or 10-bit data * autostandard, adjustment free operation * minimal external components (no loop filter components required) * isolated, quad output, adjustable cable driver * power saving secondary cable driver disable * 3.3V and 5.0V CMOS/TTL compatible inputs * lock detect indication * SMPTE scramble and NRZI coding bypass option * EDH support with GS9001, GS9021 * Pb-free and RoHS Comliant APPLICATION SMPTE 259M and 540Mb/s parallel to serial interfaces for video cameras, VTRs, and signal generators; generic parallel to serial conversion. ORDERING INFORMATION
PART NUMBER GS9032 - CVM GS9032 - CTM GS9032 - CVME3 GS9032 - CTME3 PACKAGE 44 pin TQFP 44 pin TQFP Tape 44 pin TQFP 44 pin TQFP Tape TEMPERATURE 0C to 70C 0C to 70C 0C to 70C 0C to 70C Pb-FREE AND RoHS COMPLIANT No No Yes Yes
DESCRIPTION The GS9032 encodes and serializes SMPTE 125M and 244M bit parallel digital video signals, and other 8-bit or 10-bit parallel formats. This device performs sync detection, parallel to serial conversion, data scrambling 9 4 (using the X + X + 1 algorithm), 10x parallel clock multiplication and conversion of NRZ to NRZI serial data. The GS9032 features auto standard and adjustment free operation for data rates to 540Mb/s with a single VCO resistor. Other features include a lock detect output, NRZI encoding, SMPTE scrambler bypass, a sync detect disable, and an isolated quad output cable driver suitable for driving 75 loads. The complementary cable driving output swings can be adjusted independently or the secondary differential cable driver can be powered down. The GS9032 requires a single +5 volt or -5 volt supply and typically consumes 675mW of power while driving four 75 loads.
GS9032
SYNC DETECT DISABLE (SYNC DIS)
RESET
BYPASS
10 DATA IN (PD0-PD9) 10 INPUT LATCH
SYNC DETECT
2 10 PARALLEL to SERIAL CONVERTER & NRZ to NRZI
SDO0 SDO0 SERIAL DIGITAL OUTPUTS SDO1 SDO1 SCLK/10 SCLK PLOAD SDO1 ENABLE PLL MUTE LOCK DETECT (LOCK DET) RVCO+ RVCO-
8
SMPTE SCRAMBLER
RESET BYPASS
PARALLEL CLOCK INPUT (PCLKIN) AUTO/MANUAL SELECT (AUTO/MAN) LOOP BANDWIDTH CONTROL (LBWC) DATA RATE SELECT SS[2:0]
3
BLOCK DIAGRAM
Revision Date: May 2005 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com www.gennum.com Document No. 521 - 96 - 09
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage (VS = VCC-VEE) Input Voltage Range (any input) DC Input Current (any one input) Power Dissipation (VCC = 5.25V) j-a j-c Maximum Die Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (soldering, 10 sec) VALUE 5.5V VEEGS90032
1200mW 42.5C/W 6.4C/W 125C 0C TA 70C -65C TS 150C 260C
DC ELECTRICAL CHARACTERISTICS
VCC = 5V, VEE = 0V, TA = 0 - 70C unless otherwise specified.
PARAMETER Positive Supply Voltage Power (System Power) Supply Current
SYMBOL VCC P CC
CONDITIONS Operating Range VCC = 5.0V, T = 25C (4 outputs) VCC = 5.25V (4 outputs) VCC = 5.0V, T = 25C (4 outputs) VCC = 5.25V (2 outputs) VCC = 5.0V, T = 25C (2 outputs)
MIN 4.75 2.4 2.4 -
TYP 5.00 675 135 110 -
MAX 5.25 180 160 0.8 8.0 0.8 5.0 0.4
UNITS V mW mA
NOTES
TEST LEVEL 3 5 1 3 1 7
Data & Clock Inputs (PD[9:0] PCLKIN) SYNC DIS
VIH VIL L
Logic Input High (wrt VEE) Logic Input Low (wrt VEE) Input Current Logic Input High (wrt to VEE) Logic Input Low (wrt to VEE) Input Current Sinking 500A
V V A V V A V
3
Logic Input Levels (Auto/Man, SS[2:0] Bypass, RESET)
VIH VIL L
3
Lock Detect Output TEST LEVELS
VOL
1
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1,2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product.
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AC ELECTRICAL CHARACTERISTICS
VCC = 5V, VEE = 0V, TA = 0 - 70C unless otherwise specified.
PARAMETER Serial Data Bit Rate
SYMBOL BRSDO VSDO VSDOMIN VSDOMAX tr, tf
CONDITIONS RVCO = 374 RLOAD = 37.5, RSET = 54.9 RLOAD = 37.5, RSET = 73.2 RLOAD = 37.5, RSET = 43.2 20% - 80%
MIN 143
TYP -
MAX 540
UNITS Mb/s
NOTES SMPTE 259M
TEST LEVEL 3
Serial Data Outputs Signal Swing Min. Swing (adjusted) Max. Swing (adjusted) SD Rise/Fall Times SD Overshoot/Undershoot Output Return Loss Lock Time Min. Loop Bandwidth
740
800
860
mVp-p
1
GS90032
400 -
600 1000 220
700 7 5 -
mVp-p mVp-p ps % dB ms kHz 1 1
7 1 7 7 7 6 7
ORL tLOCK BWMIN
at 540MHz Worst case 270Mb/s LBWC = Grounded : BWMIN
15 -
Typical Loop Bandwidth
BWTYP
270Mb/s LBWC = Floating :
-
500
-
kHz
7
10 BWMIN
1.7 MHz 7
Max. Loop Bandwidth
BWMAX
270Mb/s LBWC = VCC : 10 BWMIN
Intrinsic Jitter (6)
143Mb/s 177Mb/s 270Mb/s 360Mb/s 540Mb/s
LBWC = floating LBWC = VCC
-
0.07 0.07 0.08 0.09 0.11 -
NOTES
UI
3
Data & Clock Inputs (PD[9:0] PCLKIN) TEST LEVELS
tSU tH
Setup Time at 25C Hold Time at 25C
2.5 2.0
ns ns
3 3
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1,2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product.
1. Depends on PCB layout.
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PIN CONNECTIONS
SYNC DIS
RVCO+
RVCO-
LF+ LBWC
LF-
VEE
44 43 42 41 40 39 38 37 36 35
NC
VEE1
VCC1
34 33 32 31 30 29
VEE
PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PCLKIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
RESET AUTO/MAN BYPASS RSET1 VEE SDO1 SDO1 VEE SDO0 SDO0 VEE
GS90032
GS9032 TOP VIEW
28 27 26 25 24 23
SS1
LOCK DET
SSO
PIN DESCRIPTIONS
NUMBER 1-10 11 12 13 14 SYMBOL PD9 - PD0 PCLKIN VEE3 VCC3 COSC SS2, SS1, SS0 VCC2 VEE2 SDO1 ENABLE TYPE I I I DESCRIPTION CMOS or TTL compatible parallel data inputs. PD0 is the LSB and PD9 is the MSB. CMOS or TTL compatible parallel clock input. Most negative power supply connection for parallel data and clock inputs. Most positive power supply connection for parallel data and clock inputs. Master Timer Capacitor. A capacitor should be added to decrease the system clock frequency when an external capacitor is used across LF+ and LF- (NC if not used). Data rate selection when in manual mode. These pins are not used in auto mode. Most positive power supply connection for internal logic and digital circuits. Most negative power supply connection for internal logic and digital circuits. Enable pin for the secondary cable driver (SDO1 and SDO1). Connect to most negative power supply to enable. Leave open to disable (do NOT connect to VCC). TTL level which is high when the internal PLL is locked. External resistor used to set the data output amplitude for SDO0 and SDO0. Most negative power supply connection for shielding (not connected). Primary, current mode, 75 cable driving output (inverse and true) Secondary, current mode, 75 cable driving output (inverse and true) External resistor used to set the data output amplitude for SDO1 and SDO1.
15, 16, 21 17 18 19
I I
20 22 23, 26, 29 24, 25 27, 28 30
LOCK DET RSET0 VEE SDO0, SDO0 SDO1, SDO1 RSET1
O I O O I
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SDO1 ENABLE
RSET0
VEE3
COSC
VCC3
VCC2
VEE2
SS2
PIN DESCRIPTIONS
NUMBER 31 32 33 34 35 36, 38 37 39, 43 40 SYMBOL BYPASS AUTO/MAN RESET VCC1 VEE1 RVCO+, RVCONC VEE LBWC TYPE I I I I I I DESCRIPTION When high, the SMPTE Scrambler and NRZ encoder are bypassed. Autostandard or manual mode selectable operation. Resets the scrambler when asserted.
GS90032
Most positive power supply connection for analog circuits. Most negative power supply connection for analog circuits. Differential VCO current setting resistor that sets the VCO frequency. No Connect. Most negative power supply connection (substrate). TTL level loop bandwidth control that adjusts the PLL bandwidth to optimize for lowest jitter. If the pin is set to ground the loop bandwidth is BWMIN. If the pin is left floating, the loop bandwidth is approximately 3 BWMIN, if the pin is tied to VCC the loop bandwidth is approximately10 BWMIN Differential loop filter pins to optimize loop transfer performance at low loop bandwidths (NC if not used). Sync detect disable. Logic high disables sync detection. Logic low allows 8 bit operation by mapping 000-003 to 000 and 3FC-3FF to 3FF.
41, 42
LF+, LF-
I
44
SYNC DIS
I
TYPICAL PERFORMANCE CURVES (VS = 5V, TA = 25C unless otherwise shown. Guard band tested to 70C only.)
500 490 155
150 4.75 RISE 5.0 RISE 5.25 RISE 5.0 FALL
RISE / FALL TIME (ps)
480 470 460 450 4.75 FALL 440 430 420 0
CURRENT (mA)
145 5.25 140 5.0 135 4.75 130
5.25 FALL
125 20 40 60 80 0 20 40 60 80
TEMPERATURE (C)
TEMPERATURE (C)
Fig. 1 Rise/Fall Times vs. Temperature
Fig. 2 Supply Current vs. Temperature (SDO0 & SDO1 ON)
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4sc DATA STREAM SYNC DETECT 4:2:2 DATA STREAM SYNC DETECT
T R S
ACTIVE VIDEO & H BLANKING
T R S
ACTIVE VIDEO & H BLANKING
T R S
1.01
OUTPUT SWING (V)
1.005 5.25
E A V
S H BLNK A V
ACTIVE VIDEO
E A V
H BLNK
S A V
GS90032
1.000
5.0
0.995
4.75
PCLK IN
PDN XXX 3FF 000 000 XXX ***
0.99 0 20 40 60 80
***
XXX 3FF 000 000 XXX ***
TEMPERATURE (C)
SYNC DETECT
Fig. 3a Output Swing vs. Temperature (1000mV)
Fig. 5 Timing Diagram
0.8075
160 140 5.25 120
0.805
OUTPUT SWING (V)
LF+ -- LF- (mV)
0.8025 5.0 0.800 4.75
100 80 60 40
0.7975
0.795 20 0.7925 0 20 40 60 80 0
0
20
40
60
80
TEMPERATURE (C)
TEMPERATURE (C)
Fig. 3b Output Swing vs. Temperature (800mV)
Fig. 6a Loop Filter Voltage vs. Temperature (360 Mode)
40
tCLKL = tCLKH
20
LF+ -- LF- (mV)
PARALLEL CLOCK PLCK
50%
0
-20
-40
PARALLEL DATA PDn
-60
tSU
tHOLD
0
20
40
60
80
TEMPERATURE (C)
Fig. 4 Waveforms
Fig. 6b Loop Filter Voltage vs. Temperature (540 Mode)
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3500
LOOP BANDWIDTH (kHz)
3000 2500 2000 LBWC to VCC 1500 1000 500 0 LBWC FLOATING LBWC GROUNDED 0 143 177 270 360 540
GS90032
DATA RATE (Mb/s)
Fig. 7 Loop Bandwidth vs. Data Rate
Fig. 10 Output Eye Diagram (270Mb/s)
600
500
JITTER p-p (ps)
400
300
200
100 For a data rate of 270Mb/s 0 GROUNDED FLOATING VCC
LOOP BANDWIDTH CONTROL (LBWC)
Fig. 8 Output Jitter vs. LBWC
Fig. 11 Output Eye Diagram (540Mb/s)
500
400
JITTER p-p (ps)
300
200
100
0
0
100
200
300
400
500
600
DATA RATE (Mb/s)
Fig. 9 Output Jitter vs. Data Rate (Optimum LBW Setting)
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DETAILED DESCRIPTION The GS9032 Serializer is a bipolar integrated circuit used to convert parallel data into a serial format according to the SMPTE 259M standard. The device encodes both eight and ten bit TTL-compatible parallel signals producing serial data rates up to 540Mb/s. It operates from a single five volt supply and is packaged in a 44 pin TQFP. Functional blocks within the device include the input latches, sync detector, parallel to serial converter, SMPTE scrambler, NRZ to NRZI converter, internal cable driver, PLL for 10x parallel clock multiplication and lock detect. The parallel data (PD0-PD9) and parallel clock (PCLKIN) are applied via pins 1 through 11 respectively.
1. SYNC DETECTOR
about the centre frequency. The single external resistor, RVCO, sets the VCO frequency (see Figure 12).
4. VCO CENTRE FREQUENCY SELECTION
For a given RVCO value, the VCO can oscillate at one of two frequencies. When SS0=logic 1, the VCO centre frequency corresponds to the L curve. For SS0=logic 0, the VCO centre frequency corresponds to the H curve (H is approximately 1.5 x L).
800 700
GS90032
VCO FREQUENCY (MHz)
600 500 400 300 200 100 0 0 200 400 600 800 1000 1200 1400 1600 1800
The sync detector makes the system compatible with eight or ten bit data. It looks for the reserved words 000-003 and 3FC-3FF in ten bit hexadecimal, or 00 and FF in eight bit hexadecimal, used in the TRS-ID sync word. When the occurrence of either all zeros or all ones at inputs PD2-PD9 is detected, the lower two bits PD0 and PD1 are forced to zeros or ones respectively. For non-SMPTE standard parallel data, the sync detector can be disabled through a logic input, Sync Detect Disable (44).
2. SCRAMBLER
H
SSO=0
L
SSO=1
RVCO ()
Fig. 12
The scrambler is a linear feedback shift register used to pseudo-randomize the incoming serial data according to the fixed polynomial (X9+X4+1). This minimizes the DC component in the output serial data stream. The NRZ to NRZI converter uses another polynomial (X+1) to convert a long sequence of ones to a series of transitions, minimizing polarity effects. These functions can be disabled by setting the BYPASS pin (31) high.
3. PHASE LOCKED LOOP
The recommended RVCO value for auto rate SMPTE 259M applications is 374 (see the Typical Application Circuit). This value prevents false standards indication in auto mode. For non-SMPTE applications (where data rates are x2 harmonically related) use Figure 12 to determine the RVCO values. The VCO and an internal divider generate the PLL clock. Divider moduli of 1, 2, and 4 allow the PLL to lock to data rates from 143Mb/s to 540Mb/s. The divider modulus is set by the AUTO/MAN, and SS[2:0] pins (see Truth Table for further details). In addition, a manually selectable modulus 8 divider allows operation at data rates as low as 18Mb/s when RVCO is increased to 1k. When the loop is not locked, the lock detect circuit mutes the serial data outputs. When the loop is locked, the Lock Detect output is available from pin 20 and is HIGH. The true and complement serial data, SDO and SDO, are available from pins 24, 25, 27 and 28. These outputs drive four 75 co-axial cables with SMPTE level serial digital video signals. To disable the outputs from pins 27 and 28 (SDO1, SDO1), remove the resistor connected to the RSET1 pin (30) and float the SDO1 ENABLE pin (19). NOTE: Do NOT connect pin 19 to VCC. RSET calculation: 1.154 x R LOAD R SET = -------------------------------------V SDO
The PLL performs parallel clock multiplication and provides the timing signal for the serializer. It is composed of a phase/frequency detector (with no dead zone), charge pump, VCO, a divide-by-ten counter, and a divide-by-two counter. The phase/frequency detector allows a wider capture range and faster lock time than with a phase discriminator alone. The discrimination of frequency eliminates harmonic locking. With this type of discriminator, the PLL can be overdamped for good stability without sacrificing lock time. The charge pump delivers a 'charge packet' to the loop filter which is proportional to the system phase error. Internal voltage clamps are used to constrain the loop filter voltage between approximately 1.8 and 3.4 volts. The VCO is a differential low phase noise, factory trimmed design that provides increased immunity to PBC noise and precise control of the VCO centre frequency. The VCO can operate in excess of 800MHz and has a pull range of 15%
where RLOAD = RPULL-UP || Z
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TYPICAL APPLICATION CIRCUIT (SMPTE Auto Mode)
VCC J1 LBWC 374 VCC 100n
44 43 42 41 40 39 38 37 36 35 34 SYNC_DIS NC RVCO+ LBWC RVCO VCC1 LFLF+ VEE1 VEE VEE
VCC
GS90032
VCC 33 32 31 30 29 28 27 26 25 24 23 R 75 75 VCC 54.9 100n VCC 220 LOCK R L = 8.2nH R = 75 L 1 J4 L 1 J3 54.9 75 75 R L R 1 J2 L 1 J1 RESET 100n
1 PD9 2 PD8 3 PD7 4 PD6 PARALLEL DATA INPUTS 5 PD5 6 PD4 7 PD3 8 PD2 9 PD1 10 PD0 PARALLEL CLOCK INPUT
RESET AUTO/MAN BYPASS_EN RSET1 GS9032 VEE SDO1 SDO1 VEE SDO0 NC (COSC) SDO1_EN SDO0 RSET0 LOCK SS0 10k 100n SS0* 0 VEE
VCC3
VCC2
11 PCLKIN VEE3
SS2
12 13 14 15 16 17 18 19 20 21 22 SS2* SS1*
100n VCC
VCC
All resistors on ohms, all capacitors in farads, unless otherwise stated. * See Truth Table for settings. NC in auto mode.
TRUTH TABLE (Manual Mode) DATA RATE (Mb/s) 143 177 270 360 540 45 68 SS2 0 0 0 0 1 1 1 SS1 0 0 1 1 0 0 1 SS0 0 1 0 1 0 1 0 DIVIDER MODULI 4 2 2 1 1 8 8 VCO FREQUENCY H L H L H L H
SS1
VEE2
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PACKAGE DIMENSIONS
12.00 10.00
12 TYP
0.20 MIN 0 MIN 0.20 MAX RADIUS 7 MAX 0 MIN
GS90032
12.00 10.00 12 TYP 0.08 MIN. RADIUS 0.20 MIN 0.60 0.15
PIN 1
0.80
0.30
1.00
1.10
44 pin TQFP All dimensions in millimetres
0.10
0.127
REVISION HISTORY
VERSION 9 ECR 136657 DATE May 2005 CHANGES AND/OR MODIFICATIONS Removed reference to EDH FPGA core. Changed `Green' references to `RoHS Compliant'.
DOCUMENT IDENTIFICATION
DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible.
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
GENNUM CORPORATION
Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505 GENNUM UK lIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. GENNUM and the G logo are registered trademarks of Gennum Corporation. (c) Copyright 1998 Gennum Corporation. All rights reserved. Printed in Canada. www.gennum.com
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